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| SM5166AV NIPPON PRECISION CIRCUITS INC. PLL Synthesizer IC OVERVIEW The SM5166AV is a PLL synthesizer IC developed for application in pagers and fabricated using NPC's Molybdenum-gate CMOS process. It incorporates independently-controlled reference frequency and operating frequency dividers, and operates from a low-voltage supply to realize low power dissipation. It features a charge pump that operates at 3 V, making possible a wide range of VCO designs. PINOUT(TOP VIEW) XIN XOUT VDD2 DB DO VSS FIN VDD1 1 16 TEST NC OPR LE DATA CLK LD 5166AV 8 9 FEATURES s NC s s s s s s s 0.65 0.10 0.05 1.15 0.1 s s s s Operating frequency * fFIN = 100 MHz (VDD1 = 1.00 V) * fFIN = 90 MHz (VDD1 = 0.95 V) Reference frequency * fXIN = 25 MHz (VDD1 = 0.95 V, External Input) * fXIN = 16 MHz* (VDD1 = 0.95 V, Internal oscillaton) NOTE) * : NPC's recommended frequency. Confirm with crystal supplier. Unlock signal output pin Output circuit for passive filter connection -10 to 60 C operating temperature range Standby function for low current consumption Boost-up signal output for fast locking Supply voltages * VDD1 = 0.95 to 1.5 V (prescaler, counters) * VDD2 = 2.0 to 3.3 V (charge pump) 40 to 65528 reference frequency divider ratio range (with 1/8 prescaler built-in) set by serial input data 1056 to 65535 operating frequency divider ratio range set by serial input data 16-pin VSOP Molybdenum-gate CMOS process PACKAGE DIMENSIONS Unit: mm 16-pin VSOP 4.4 0.2 6.4 0.2 5.1 0.2 0.15 - + 0.10 0.05 0 10 + 0.10 0.22 - 0.05 0.5 0.2 NIPPON PRECISION CIRCUITS--1 SM5166AV BLOCK DIAGRAM TEST LD XIN XOUT 1/8 PRESCALER 13 BIT R COUNTER LEVEL SHIFTER VDD1 AREA VDD2 DATA CLK LE VDD2 AREA 14 BIT LATCH LOCK DETECTOR 16 BIT SHIFT REGISTER PHASE DETECTOR LATCH SELECTOR BOOSTER S. G. DB 16 BIT LATCH OPR LEVEL SHIFTER CHARGE PUMP DO VDD1 FIN VDD1 AREA LEVEL SHIFTER 16 BIT N COUNTER VSS WINDOW GENERATOR PIN DESCRIPTION Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name XIN XOUT VDD2 DB DO VSS FIN VDD1 NC LD CLK DATA LE OPR NC TEST I/O I O - O O - I - - O I I I I - I Description Reference frequency divider crystal (oscillator) connection pins. Alternatively, an external clock input can be connected to XIN. The clock is also output on XOUT. Feedback resistor built-in for AC-coupled inputs. Phase detector, charge pump and boost-up signal 3 V supply boost-up signal output for faster locking Phase detector output pin. Built-in charge pump and tristate output means that this output can be connected to a low-pass filter. The output polarity is preset for connection to a passive filter. Ground pin Operating frequency divider input pin. Feedback resistor built-in for AC-coupled inputs. Reference frequency and operating frequency prescaler and counter 1 V supply No connection Unlock signal output pin. (Unlocked when HIGH) The function of LD can be turned OFF using the LD input control bit (LD should be tied LOW when not used). Control data clock input pin Control data input pin Control data latch enable signal input pin Power-save control pin. Start when HIGH, standby mode when LOW. No connection Test pin. Pull-down resistor built-in. Leave open or connect to ground for normal operation. NIPPON PRECISION CIRCUITS--2 SM5166AV SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V Parameter Supply voltage Symbol V DD1 V DD2 Input voltage range Storage temperature range Power dissipation Soldering temperature Soldering time V IN1 V IN2 Tstg PD Tsld tsld VDD1 VDD2 FIN, XIN, TEST OPR, CLK, DATA, LE Pin name Rating -0.3 to 2.0 -0.3 to 7.0 V SS - 0.3 to V DD1 + 0.3 V SS - 0.3 to V DD2 + 0.3 -40 to 125 150 255 10 Unit V V V V C mW C s Recommended Operating Conditions VSS = 0 V Parameter Supply voltage Operating temperature range Symbol V DD1 V DD2 Topr Condition Rating 0.95 to 1.5 2.0 to 3.3 -10 to 60 Unit V V C Electrical Characteristics VSS = 0 V, VDD1 = 0.95 to 1.5 V, VDD2 = 2.0 to 3.3 V, Ta = -10 to 60 C Rating Parameter Symbol Note 1. VDD1 operating current consumption VDD2 standby current IDD1 IDD2 Note 2. Note 3. V DD1 = 0.95 to 1.50 V V DD1 = 1.00 to 1.50 V Condition min - - - 90 100 25 - - 0.3 0.3 0.3 - typ 0.70 0.75 0.01 - - - - - - - - - max 1.10 mA 1.20 10.0 - MHz - - 40 9 - Vp-p V DD1 = 1.00 to 1.50 V, fFIN = 100 MHz, AC coupling fXIN = 25 MHz sine wave, AC coupling (external input) - - 0.3 Vp-p V MHz MHz MHz A Unit FIN maximum operating input frequency fmax1 300 mVp-p sine wave XIN maximum operating input frequency FIN minimum operating input frequency XIN minimum operating input frequency fmax2 fmin1 fmin2 300 mVp-p sine wave (external input) 300 mVp-p sine wave 300 mVp-p sine wave (external input) V DD1 = 0.95 to 1.50 V, fFIN = 90 MHz, AC coupling FIN input amplitude V FIN XIN input amplitude OPR, CLK, DATA, LE LOW-level input voltage V XIN V IL NIPPON PRECISION CIRCUITS--3 SM5166AV Rating Parameter OPR, CLK, DATA, LE HIGH-level input voltage FIN LOW-level input current XIN LOW-level input current FIN HIGH-level input current XIN HIGH-level input current DO, DB LOW-level output current DO, DB HIGH-level output current Tristate output high-impedance leakage current DATA CLK setup time CLK LE setup time Hold time Symbol Condition min V IH IIL1 IIL2 IIH1 IIH2 IOL IOH IOZL IOZH tSU1 tSU2 tH See the timing diagrams. V IL = 0 V 1.5 - - - V IH = V DD1 Note 4. Note 5. VOL = 0 V VOH = V DD2 - 1.0 1.0 - - 2 2 2 typ - - - - - - - - - - - - max - 60 10 60 10 - - 100 100 - - - V A A A A mA mA nA nA s s s Unit 1. V DD1 = 0.95 to 1.05 V, V DD2 = 2.7 to 3.3 V, fFIN = 90 MHz (300 mVp-p sine wave), fXIN = 14.4 MHz (300 mVp-p sine wave), OPR = HIGH, no output load 2. V DD1 = 1.00 to 1.05 V, V DD2 = 2.7 to 3.3 V, fFIN = 100 MHz (300 mVp-p sine wave), fXIN = 14.4 MHz (300 mVp-p sine wave), OPR = HIGH, no output load 3. V DD1 = 0 V, V DD2 = 2.7 to 3.3 V, OPR = LOW, no input/output load (i.e. CLK = DATA = LE = 0 V) 4. DO and DB outputs are derived from the VDD2 supply. V DD2 = 2.7 to 3.3 V, VOL = 0.4 V 5. DO and DB outputs are derived from the VDD2 supply. V DD2 = 2.7 to 3.3 V, VOH = V DD2 - 0.4V DATA, CLK, and LE timing DATA VIH VIH tSU1 CLK VIH tH tSU2 LE VIH NIPPON PRECISION CIRCUITS--4 SM5166AV FUNCTIONAL DESCRIPTION Operating Frequency Divider (N-counter) Structure The operating frequency divider generates a comparator frequency signal (FV), which is input to the phase comparator, by dividing the VCO signal input on pin FIN. The operating frequency divider is comprised by dual modulus prescalers, a 5-bit swallow counter and a 11-bit main counter. The settings for the prescaler (P and P + 1), swallow counter (S) and main counter (M) are related to the comparator frequency divider ratio by: N = (P + 1) x S + P(M - S) = PM + S The counter value ranges are P = 32, P + 1 = 33, S = 0 to 31, and M = 32 to 2047. Therefore, the operating frequency divider ratio range N is 1056 to 65535. Input Data The input data should be specified keeping in mind the VDD2 supply. The data is input using CLK, DATA and LE pins into the shift register and latch which operate from the VDD2 supply. However, the VDD1 supply level can vary. The control data input uses a 3-line 17-bit serial interface comprising the clock (CLK), data input (DATA) and latch enable (LE). The data is input with the MSB first. The last (17th) bit is used as the latch select control bit. Data is written to the shift register on the rising edge of the clock signal. Accordingly, the data should change state on the falling edge of the clock signal. Data is transferred from the shift register to the latch when the latch enable (LE) signal goes HIGH. Accordingly, the latch enable signal should be held LOW while data is being written to the shift register. The clock and data input signals are both ignored when the latch enable signal goes HIGH. Also, the CLK, DATA and LE inputs should be tied LOW when not setting data. Reference Frequency Divider (R-counter) Structure The reference frequency divider generates a comparator frequency signal (FR), which is input to the phase comparator, by dividing the reference frequency input either from an external signal on XIN or from a crystal connected between XIN and XOUT. The reference frequency divider is comprised by a fixed divide-by-8 prescaler and an 13-bit reference counter. The settings for the prescaler (A = 8) and reference counter (R) are related to the reference frequency divider ratio by: R = AB = 8B The counter value ranges are A = 8 and B = 5 to 8191. Therefore, the reference frequency divider ratio range is R = 40 to 65528. NIPPON PRECISION CIRCUITS--5 SM5166AV Input Data Format Shift register timing CLK 1 DATA MSB 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 LSB CONTROL LE Figure 1. Comparator data format Latch select The last (17th) data bit determines the status of the shift register data latch. Table 1. Latch select bit function Bit 17 0 Latch Swallow counter and main counter frequency divider ratio latch select Reference frequency counter divider ratio data and LD output latch select 1 Swallow counter and main counter frequency divider MSB LSB DATA 1 210 2 29 3 28 4 27 5 26 6 25 7 24 8 23 9 22 10 21 11 20 12 24 13 23 14 22 15 21 16 20 17 Main counter Swallow counter (11-bit : 32 to 2047) (5-bit : 0 to 31) Latch selection bit : Set to "0" Figure 2. Swallow counter and main counter frequency divider data format Input data example If the VCO output (fVCO) is trebled, the output frequency (fLO) is 251.3 MHz, and the channel bandwidth (fCH: operating frequency (fR) x 3) is 25 kHz, then the comparator frequency divider ratio N is given by: f LO f VCO x 3 251.3 3 N = --------- = ----------------------- = ------------------- = 10052 = 32 x 314 + 4 f CH fR x 3 0.025 3 Therefore, the swallow counter count is 4 (00100)2 and the main frequency divider counter count is 314 (0000100111010)2. The input data format is shown in figure 3. NIPPON PRECISION CIRCUITS--6 SM5166AV MSB LSB 1 210 Input Data 0 2 29 0 3 28 1 4 27 0 5 26 0 6 25 1 7 24 1 8 23 1 9 22 0 10 21 1 11 20 0 12 24 0 13 23 0 14 22 1 15 21 0 16 20 0 17 0 Main counter Swallow counter (11-bit : 32 to 2047) (5-bit : 0 to 31) Latch selection bit : Set to "0" Figure 3. Swallow counter and main counter frequency divider data example Reference counter frequency divider setting MSB LSB DATA 1 212 2 211 3 210 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 15 16 17 (Reference counter 13-bit : 5 to 8191) LD output setting bit Test bits : (15, 16) = (0, 0) for normal operation Latch selection bit : Set to "1" : Normal operation when 1, LOW-level output when 0. Figure 4. Reference counter data and LD output setting format Input data example If the VCO output (fVCO) is trebled, the crystal frequency is 12.8 MHz and the channel bandwidth (fCH: comparator frequency (fR) x 3) is 25 kHz, then the reference frequency divider ratio R is given by: Xtal Xtal 12.8 NR = ---------- = -------------- = ------------------- = 1536 = 8 x 192 f CH fR x 3 0.025 3 Therefore, the reference counter count is 192 (00011000000)2. The input data format is shown in figure 5. NIPPON PRECISION CIRCUITS--7 SM5166AV MSB LSB 1 212 Input Data 0 2 211 0 3 210 0 4 29 0 5 28 0 6 27 1 7 26 1 8 25 0 9 24 0 10 23 0 11 22 0 12 21 0 13 20 0 14 15 16 17 1 0 0 1 (Reference counter 13-bit : 5 to 8191) LD output setting bit Test bits : (15, 16) = (0, 0) for normal operation Latch selection bit : Set to "1" Figure 5. Reference counter data and LD output setting example NIPPON PRECISION CIRCUITS--8 SM5166AV Boost-up Signal If the PLL momentarily loses lock as a result of a phase error, a level signal is output on pin DB. When the PLL is operating in lock, output DB goes high impedance. When the PLL starts up, the signal on DB charges the low-pass filter capacitor in anticipation of highspeed locking. After the boost-up signal is output and the PLL phase error comes within tolerance, the boost-up circuit stops and operation continues when the 2 supplies (VDD1, VDD2) are applied and OPR goes HIGH once only. After the boost-up circuit stops, new data is written and the boost-up signal is not output even if the VCO is not in lock. Operating principles When the PLL is operating with a phase error within fixed tolerance, an internal WINDOWN signal is generated, as shown in figure 6. This signal is in sync with the N counter output signal (FV) and is 64 cycles of the FIN input period in length centered about the falling edge of FV. If the phase detector error correction signal occurs before the WINDOWN LOW-level pulsewidth, the HIGH-level output from DB continues. However, if the error correction signal occurs wholly within the WINDOWN LOW-level pulsewidth, DB goes high impedance and the boost-up circuit operation stops. The above description applies when the error correction signal is revising up. When the error correction signal is revising down, DB goes LOW. FR FV Phase Detector error correction signal WINDOWN ( : 32fFIN ) DB Hi-Impedance HIGH level output Hi-Impedance Figure 6. boost-up signal timing Standby Mode The SM5166AV enters standby mode when OPR goes LOW. In this mode, the states and functions shown in table 2 occur. In standby mode, some current flows into VDD1 (FIN and XIN prescaler current). Therefore, it is necessary to reduce VDD1 to 0 V to fully reduce current consumption and reduce power dissipation. Table 2. Standby mode block states Block DO and DB LD Phase comparator Input FIN Input XIN N counter R counter Latch data State Floating (high impedance) LOW-level output Reset Feedback resistor is cutoff (HIGH level) Feedback resistor is cutoff (HIGH level) Reset Reset Stored (while V DD2 is within rating) NIPPON PRECISION CIRCUITS--9 SM5166AV Phase Comparator Timing Diagram The DO output circuit polarity is configured for connection to an external passive filter. The signals compared are FV and FR, which are the internal operating frequency divider output signal and reference frequency divider output signal, respectively. The timing and passive filter basic structure are shown in figures 7 and 8, respectively. FR FV DO LD Figure 7. Phase detector timing R1 DO R2 C Figure 8. Passive filter VCO NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, 2-chome Fukuzumi Koutou-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9610BE 1997.05 NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS--10 SM5166AV INPUT/OUTPUT EQUIVALENT XIN, XOUT CIRCUITS DO VDD2 XOUT From Internal Circuit VDD1 VDD1 Lagging Phase Correction Signal Leading Phase Correction Signal DO XIN Internal Circuit To Internal Counter LD VDD1 From Internal Circuit VDD2 From Internal Circuit LD Transistor Resistor FIN VDD1 From Internal Circuit DB VDD1 VDD2 To Internal Counter From Internal Circuit From Internal Circuit FIN1 DB Diffused Resistor OPR, CLK, DATA, LE VDD2 TEST VDD1 VDD1 To Internal Circuit OPR CLK DATA LE To Internal Circuit TEST Transistor Resistor NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, 2-chome Fukuzumi Koutou-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9610BE 1997.05 NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS--11 |
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